Blowable memory device and method of blowing such a memory

ABSTRACT

A memory device includes a plurality of memory cells arranged as a matrix. Each memory cell includes a transistor and a capacitor connected in series. Each memory cell is linked to a bit line that connects the memory cells of a column. Each memory cell is also linked to a word line and to a third line. A gate of the transistor of a memory cell is linked to the word line, with each word line being linked to the gates of the transistors in a respective column. A third line is linked to the sources of the transistors of a row of memory cells. A bit line is linked to the capacitors of the transistors of a column. The voltage between the gate and the source of a transistor can thus be controlled via the word column and the third line.

FIELD OF THE INVENTION

[0001] The present invention relates to the field of electronics, andmore particularly, to an integrated memory comprising a plurality ofmemory cells arranged as a matrix with row and column addressing.

BACKGROUND OF THE INVENTION

[0002] Reference may be made to the article “A Survey of CircuitInnovations in Ferroelectric Random-Access Memories” by AliSheikholeslami and P. Glenn Gulak, in Proceedings Of The IEEE, Vol. 88,No. 5, May 2000, which describes various types of memories. Withreference to FIG. 23 of this article, a block diagram of a nonblowable,conventional ferroelectric memory comprising a matrix of memory cells isdescribed therein.

[0003] The addressing is achieved via a column-wise bit line and a wordline and a plate line per row. The word line of a row is arranged on oneside of the memory cells of the row, while the plate line is arranged onthe opposite side, adjacent to the word line of the next row. Eachmemory cell comprises a MOS transistor whose gate is linked to the wordline, a drain linked to the bit line and a source linked to thecapacitor. The other terminal of the capacitor is linked to the plateline.

[0004] In the field of blowable memories, one seeks to blow thecapacitors of specified memory cells without harming the neighboringmemory cells using a voltage greater than the normal operating voltage.By way of example, in a circuit whose normal operating voltage is 3.3volts, a voltage of 6 volts is applied to one of the addressing lines,and the transistor of the memory cell to be blown is turned on. Theother addressing line is set to 0 volts so that the capacitorexperiences a voltage of 6 volts sufficient to blow it.

[0005] Stated otherwise, its characteristics are irretrievably modified.In known memories, the application of the blowing voltage results inexcessive voltages across the terminals of the neighboring cells whichcould be damaged depending on the ratio of impedance between thecapacitor and the transistor of each memory cell.

SUMMARY OF THE INVENTION

[0006] In view of the foregoing background, an object of the presentinvention is to provide a highly reliable blowable memory architectureso that the blowing of a memory cell does not negatively affect theother memory cells.

[0007] This and other objects, advantages and features according to thepresent invention are provided by a blowable memory device comprising aplurality of memory cells arranged as a matrix, with each memory cellcomprising a transistor and a capacitor connected in series, and islinked to a bit line linked to the memory cells of a column, to a wordline and to a third line. The gate of the transistor of a memory cell islinked to the word line. A third line is linked to the sources of thetransistors of a row of memory cells, a bit line is linked to thecapacitors of the transistors of a column of memory cells and a wordline is linked to the transistors of a column of memory cells to form aword column so that the voltage seen by the transistor can be controlledvia the word column and the third line.

[0008] In one embodiment of the invention, each third line is equippedwith a driver for providing a voltage on the third line. In anotherembodiment of the invention, the memory device comprises a predecodingmodule connected to the drivers for providing a voltage on the thirdlines. Advantageously, each driver may provide a first voltage or asecond voltage on a third line.

[0009] In another embodiment of the invention, the memory devicecomprises a decoding module for controlling a plurality of word columnsand a decoding module for controlling a plurality of bit lines. Thedevice may comprise at least one blowable type capacitor.

[0010] The device may comprise multiplexing means provided with a moduleper bit line and evaluation means. The modules selectively link a memorycell to the evaluation means. The evaluation means outputs a logic levelcorresponding to the impedance of the memory cell selected.

[0011] The invention also provides a method of blowing a capacitor of amemory cell, wherein each memory cell comprises a capacitor and atransistor connected in series. The method comprises providing a highvoltage V₁ on a terminal of the capacitor, an intermediate voltage V₂ onthe gate of the transistor, and a low, zero or negative voltage V₃ onthe source of the transistor. This is done while providing the highvoltage V₁ on the terminals of the capacitors of the memory cells of thesame column, and an intermediate voltage V₄ on the sources of thetransistors of the other rows.

[0012] Thus, only the capacitor of the memory cell which one chooses toblow receives at its terminals a sizeable voltage, close to thedifference V₁−V₃, while the elements of the other memory cells receiveat their terminals voltages close to the normal operating voltage.Advantageously, the intermediate voltage V₂ is imposed on the gates ofthe transistors of the same column. In one embodiment of the invention,the voltages V₂ and V₄ are equal. We can have V₃=0 volts and V₂ and V₄close to V₁/2. More precisely, provision may be made for V₂ and V₄ tolie between 40 and 60% of the value of V₁, and preferably between 50 and60%. By way of example, V₁ may be equal to 6 volts, V₂ and V₄ may beequal to 3.3 volts and V₃ may be equal to 0 volts.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention will be better understood on studying thedetailed description of a few embodiments taken by way of nonlimitingexamples and illustrated by the appended drawings, in which:

[0014]FIG. 1 is a block diagram of a memory device according to thepresent invention;

[0015]FIG. 2 is a more detailed block diagram according to the presentinvention in which the drivers and the decoding modules have beenrepresented;

[0016]FIG. 3 is a diagram of means for reading the memory deviceaccording to the present invention; and

[0017]FIGS. 4 and 5 are partial diagrams respectively illustrating thereading of a capacitor in the blown state and in the nonblown stateaccording to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] As illustrated in FIG. 1 a memory device is referenced 1 as awhole, but only a part of which has been illustrated. The memory device1 comprises a plurality of memory cells CM arranged in rows and columns.The memory cell of column i and row j is denoted CM_(i,j). Each memorycell CM is linked to a bit line BL arranged vertically in FIG. 1, andtherefore serving the memory cells of a column.

[0019] Also provided are word columns WC that are arranged verticallyand serving the memory cells CM of a column, source lines SL that arearranged horizontally and serving the memory cells CM of a row. Statedotherwise, the memory cell CM_(i,j) of column i of row j is linked tothe bit line BL_(i), to the word column WC_(i) and to the source lineSL_(j).

[0020] More precisely, the gate of the transistor T_(i,j) of the memorycell CM_(i,j) is linked to the word column WC_(i) of the column to whichthe memory cell belongs, while the source of the transistor T_(i,j) islinked to the source line SL_(j) of the row to which the memory cellCM_(i,j) belongs. The capacitor C_(i,j) of the memory cell CM_(i,j) islinked to the drain of the transistor T and to the bit line BL_(i) ofthe column to which the memory cell CM_(i,j) belongs.

[0021] In FIG. 1, the capacitors CM_(i,j+1), CM_(i+1,j+1) andCM_(i+2,j+1) have already been blown and are represented in a particularmanner with a rectangle between the two segments depicting thecapacitor. The blowing of the capacitor C_(i,j) of memory cell CM_(i,j)is performed as follows. A high voltage V₁, for example 6 volts, isapplied to the bit line BL_(i). An intermediate voltage V₂ is applied tothe word column WC_(i), with V₂ equal to 3.3 volts, for example. Thevoltage V₃, for example zero, is applied to the source line SL_(j).Furthermore, an intermediate voltage V₄, for example 3.3 volts, isapplied to the source lines other than the source line SL_(j), and a lowor zero intermediate voltage is applied to the bit lines other than theline BL_(j). A zero voltage is applied to the word columns other thanthe word column WC_(j).

[0022] As a result, the transistor T_(i,j) receives on its source avoltage V₃ which is sufficiently below the voltage which it receives onits gate to turn it on, so that the drain of the transistor T_(i,j) isat a voltage close to the voltage V₃. The capacitor C_(i,j) experiencesa voltage close to the difference V₁−V₃ which is sufficient to blow it.The transistors of the same column, for example the transistorT_(i,j+1), has a voltage between its gate and its source V_(gs)=V₂−V₄which is almost zero. In any event, the voltage is such that thetransistor T_(i,j+1) is off. The voltage across the terminals of thememory cell CM_(i,j+1) is equal to the difference V₁−V₄, for example, onthe order of 2.7 volts. This voltage can be entirely withstood by thetransistor T_(i,j+1), or more generally, by one of the two elementsforming the memory cell CM_(i,j+1).

[0023] The memory cell CM_(i+1,j) of the same row as the memory cellCM_(i,j) which is blown receives the following voltages: a voltage V₃,for example zero, on the source line SL_(j), a voltage which wouldgenerally be chosen to be zero on the word column WC_(i+1), and avoltage which may likewise be chosen to be zero on the bit lineBL_(i+1). It is understood that there is no particular danger ofdamaging the memory cell CM_(i+1,j) of the same row as the memory cellCM_(i,j) in the course of blowing the memory cell. More generally, withthe source line SL_(j) being close to 0 volts, any voltage lying between0 volts and the normal operating voltage, for example 3.3 volts, may beapplied without damaging or providing any particular drawback to theword column WC_(i+1) and to the bit line BL_(i+1).

[0024] In the present architecture, a transistor of column i and of arow different from j during the blowing of the memory cell CM_(i,j)experiences a voltage which is equal to the maximum between the voltageV₂ and the difference V₁−V₂. Specifically, the voltage between the gateand the drain is equal to V_(gd)=V₁−V₂/V_(gs), with V_(gs)=V₂.

[0025] By way of example, with a voltage V₁ of 6 volts and a voltage V₂and V₄ of 3.3 volts, a transistor T is able to withstand 3.3 voltsmaximum between its gate and source, its gate and drain and its gate andbase, and can still operate. The transistor receives 3.3 volts maximumat its terminals and is not stressed or damaged, while in otherarchitectures it would experience 6 volts and might be stressed ordamaged. Hence, V₁ will be chosen to be sufficiently high to blow thecapacitors while remaining less than twice the supply voltage of astandard MOS transistor.

[0026] Represented in FIG. 2 are the drivers P of each source line SL.Driver P_(j) linked to source line SL_(j) is able to impose either thevoltage V₃ or the voltage V₄ on the line SL_(j) while providing thenecessary current for obtaining the voltage. By way of example, driverP_(j) will be able to impose a zero voltage or a voltage equal to 3.3volts. A plurality of drivers P are linked to a predecoding modulereferenced 2, which makes it possible to generate the control commandsrequired for the various drivers P on the basis of a control wordreceived by the predecoding module 2 and originating from elementsoutside the memory. The predecoding module 2 may be of a conventionaltype.

[0027] By virtue of the invention, a memory architecture is madeavailable which is very well tailored to blowable memories and allowsthem to be produced in numerous technologies, includingovervoltage-sensitive MOS technologies. This does away with the need forMOS transistors which are very robust to overvoltages and which aregenerally more bulky and more expensive.

[0028] The reading of such a memory is performed by evaluating theimpedance of the capacitor C which is different depending on whether itis intact or blown. For the reading of the memory cell CM_(ij), it ispossible to send a first reading voltage on the bit line BL_(i), asecond reading voltage on the word column WC_(i), and a zero voltage orone close to zero on the source line SL_(j) and another voltage, forexample equal to the second reading voltage on the source lines of theother rows different from row j.

[0029] A reading device embodiment is described with reference to FIG. 3in which four memory cells CM_(i,j), CM_(i,j+1), CM_(i+1,j),CM_(i+1,j+1) have been represented. The end of each word line WC islinked to a driver PW. Each driver PW_(i) is controlled by a selectionline Sel_(i). The drivers of the source lines SL have not beenrepresented. The end of each bit line BL is linked to a read/writemodule MB. Several read/write modules MB are linked to an evaluationmodule ME.

[0030] The read/write module MB_(i) comprises an element 3 of thethree-stage buffer type. The output of the element 3 is linked to thebit line BL_(i), and an input is linked to a programming line Prog andanother input is linked to the selection line Sel_(i). The read/writemodule MB_(i) also comprises a MOS transistor 4 and an AND logic gate 5.The AND logic gate 5 includes an output linked to the gate of thetransistor 4, an input linked to the selection line Sel_(i) and anotherinput linked to a read control line Lec. The transistor 4 is linked tothe bit line BL_(i) and to a line 6 common to several bit lines BL andlinked to the input of the evaluation module ME.

[0031] The evaluation module ME comprises two MOS transistors 7 and 8, aresistor 9 and a driver 10. The gates of the two transistors 7 and 8 arelinked to the line 6. The drains of the two transistors 7 and 8 arelinked to a voltage source Vdd. The source of the transistor 7 is alsolinked to the line 6. The source of the transistor 8 is linked to theresistor 9, the other terminal of which is grounded, and to the input ofthe driver 10. The output of the driver 10 forms the output of theevaluation module ME.

[0032] The manner of operation is as follows. When the Prog line is atthe logic value 0, the output of the elements 3 are an open circuit.That is, the lines BL are at a voltage independent of the correspondinglines Sel_(i), reading is possible and writing is disabled. When theProg line is at the logic value 1, the lines BL may be at 1 andprogramming access is possible, depending on the logic value of the lineSel_(i). If Sel_(i) is at the logic value 1 then the output of theelement 3 of column i takes the logic value 1. Provision is made for thelogic value 1 at the output of the elements 3 to be high, and inparticular, equal to V₁. Thus, to blow a memory cell CM of column i, thelines Prog and Sel_(i) are set to the 1 logic value level.

[0033] If Prog is at a logic value 1 and Sel_(i) is at a logic value 0,then the output of the element 3 of column i is at the logic value 0 andimposes it on the line BL_(i). When the line Lec is at the logic value0, the gates of the transistors 4 are at the logic value 0, thetransistors 4 are off and read access is disabled. When the line Lec isat the logic value 1, the gates of the transistors 4 may be at 1, thetransistors 4 may be at 1 and read access is possible depending on thelogic value of the line Sel_(i) which will permit or disallow thereading of the memory cells of column i.

[0034] When Lec is at a logic value 1, a single line Sel may be at alogic value 1 at a given instant for a module ME. When Sel_(i) is at alogic value 1 and Lec is at a logic value 1, the gate of the transistor4 of the module MB_(i) is at the logic value 1 and the transistor 4 ison. The driver PW_(i) controlled by the line Sel_(i) sends a voltageover the line WC_(i) such that the transistors T_(i) of the memory cellsCM_(i) may be on. Simultaneously, the source line SL_(j) is set to a lowor zero voltage and the other source lines SL_(j) are set to a voltageon the order of V₂, so that the transistor T_(i,j) is on and the othertransistors T_(i,j) of column i are off.

[0035] Thus, only the transistor T_(i,j) is on and all the othertransistors dependent on the same module ME are off. It follows that thecurrent passing through the transistor T_(i,j) is equal to the currentpassing through the transistor 4 of the module MB_(i) and to the currentflowing through the input of the module ME.

[0036] The capacitor C of the transistor T_(i,j) exhibits an impedanceZ_(c) in the blown state and Z_(n) in the normal, nonblown state. Themanner of operation in the two states is represented in FIGS. 4 and 5.As described above, during reading, the transistor T_(i,j) and thetransistor 4 of the module MB_(i) are on. To the impedance Z_(c) therecorresponds a current I_(c) in the transistor 8 and the resistor 9, anda voltage U_(c) at the point common to the transistor 8 and to theresistor 9. To the impedance Z_(n) there corresponds a current I_(n) inthe transistor 8 and the resistor 9, and a voltage U_(n) at the pointcommon to the transistor 8 and to the resistor 9. The driver 10 thenmakes it possible to output voltage values at the levels required by theremainder of the circuit or of other circuits. The module ME makes itpossible to read the impedance of the memory cells to which it is linkedand to translate an impedance into a logic level.

[0037] Stated otherwise, the device comprises multiplexing meansprovided with a module per bit line and an evaluation means. The modulesselectively link a memory cell to the evaluation means, and theevaluation means output a logic level corresponding to the impedance ofthe memory cell selected. A single evaluation means is associated withmemory cells of a plurality of columns.

That which is claimed is:
 1. Memory device (1), comprising a pluralityof memory cells (CM) arranged as a matrix, each memory cell comprising atransistor (T) and a capacitor (C) in series, and being linked to a bitline (BL) linked to the memory cells of a column, to a word line and toa third line (SL), the gate of the transistor of a memory cell beinglinked to the said word line, characterized in that at least one thirdline (SL) is linked to the sources of the transistors of a row of memorycells, a bit line (BL) being linked to the capacitors of the transistorsof a column and a word line being linked to the transistors of a columnso as to form a word column (WC), in such a way that the voltage betweenthe gate and the source of a transistor can be controlled via the wordcolumn and the third line.
 2. Device according to claim 1, characterizedin that each third line is equipped with a driver (P) able to impose avoltage on the said third line.
 3. Device according to claim 2,characterized in that it comprises a predecoding module (2) able tocontrol a plurality of drivers of third lines.
 4. Device according toclaim 2 or 3, characterized in that a driver is capable of imposing afirst voltage or a second voltage on the said third line.
 5. Deviceaccording to any one of the preceding claims, characterized in that itcomprises a decoding module linked to the word columns and a decodingmodule linked to the bit lines.
 6. Device according to any one of thepreceding claims, characterized in that at least one capacitor isblowable.
 7. Device according to any one of the preceding claims,characterized in that it comprises a multiplexing means provided with amodule (MB) per bit line (BL) and an evaluation means (ME), themultiplexing means being able to selectively link a memory cell to theevaluation means.
 8. Device according to claim 7, characterized in thatthe evaluation means is able to output a logic level corresponding tothe impedance of the memory cell selected.
 9. Method of blowing acapacitor of a memory cell comprising a capacitor and a transistor inseries, in which a high voltage V₁ is imposed on a terminal of the saidcapacitor, an intermediate voltage V₂ is imposed on the gate of the saidtransistor, and a low, zero or negative voltage V₃ is imposed on thesource of the said transistor, while imposing the high voltage V₁ on theterminals of the memory cells of the same column, an intermediatevoltage V₄ on the sources of the transistors of the other rows. 10.Method according to claim 9, in which the intermediate voltage V₂ isimposed on the gates of the transistors of the same column.